Workshop

Prof. Mark J. Kushner (University of Michigan)

Overview of Integrated Plasma Reactor and Feature Scale Modeling: Algorithms and Applications to Cryogenic Etching

There are great expectations for the role of the digital twin (DT) in the development of plasma processes for semiconductor device fabrication. Although surrogate models will play an important role in the DT, surrogate models will depend on physics based models for training data. This is particularly the case for integration of plasma reactor scale processes with the surface chemistry occurring during etching of high aspect ratio (HAR) features. In this presentation, an overview of integrated plasma reactor and feature modeling will be provided. The emphasis will be on the algorithms required to represent reactive fluxes (and their energy distributions) to wafers given the complexity of the state-of-the-art plasma tools now in (or soon to be in) fabrication facilities. The algorithms and mechanisms for feature scale processes for HAR etching will be discussed with applications to cryogenic etching.

Prof. Yoshihiro Kangawa (Kyushu University)

Optimal Design of MOCVD Process for AlGaN/AlN Deep-Ultraviolet Laser Diodes: Ab Initio-Based Approach

Deep ultraviolet (DUV) light near 260 nm, which is absorbed by RNA and DNA in viruses and bacteria, is expected to be useful. To enhance the emission efficiency of DUV-LDs and LEDs, controlling the flatness of the AlGaN/AlN heterointerfaces in the device structure at the atomic level is essential. In this talk, I will discuss the relationship between the device fabrication process, specifically the thin-film growth temperature, and the flatness of the heterointerface using an ab initio-based approach.

Prof. Lado Filipovic (Vienna University of Technology)

Process Topography TCAD for Advanced Manufacturing

This talk discusses recent perspectives on process topography TCAD, focusing on computational methods for modeling evolving surfaces during semiconductor fabrication steps such as deposition, etching, and pattern transfer. Particular attention will be given to algorithmic challenges in moving-interface representation and flux/visibility calculations, including the role of ray tracing in feature-scale process modeling. The talk will also discuss opportunities enabled by GPU acceleration and emerging forms of AI integration, including surrogate modeling, workflow acceleration, and data-assisted calibration for predictive and scalable TCAD.

Dr. Yury Shustrov (STR Software)

Multiscale Modeling of SiGe-based Device Processing

Si/SiGe heterostructures enable leading-edge and emerging devices including gate-all-around and CFET transistors, next-generation 3D-DRAM, and spin qubits. Their fabrication demands precise control over layer thickness, interface sharpness and selective-etch fidelity at both wafer and atomic scales.

In this talk, I will present a multi-scale modeling framework spanning five orders of magnitude, from centimeter to nanometer, that combines chamber-scale CFD simulations of epitaxy and etching with atomic- and feature-scale models of growth, interface formation, dislocation evolution and etching processes. At the wafer scale, the epitaxy models reproduce the dependence of Si and SiGe growth rate and uniformity on recipe parameters across 300 mm wafers with accuracy suitable for process optimization. At the nm scale, predicted interface sharpness agrees with SIMS measurements. For SiGe selective etching, the chamber-scale model is coupled to a feature-scale model that reproduces selectivity and profile evolution in representative gate-all-around FET structures. The framework presented provides a link from recipe parameters to as-fabricated device geometry.

Prof. Marco Pala（DPIA, University of Udine, Italy）

Ab initio Transport in 2D Materials Heterojunction Devices

This talk will investigate the transport properties of nanodevices based on 2D materials heterostructures using a fully ab initio approach. This methodology combines density functional theory (DFT) to describe the material properties with the non-equilibrium Green's function (NEGF) formalism to model quantum transport in nanostructures and electron devices.

The simulation workflow consists of computing plane-wave Hamiltonians with a DFT solver, transforming them into a reduced basis composed of unit-cell restricted Bloch functions (UCRBF) and finally solving the kinetic equations for Keldysh Green's functions. This approach enables full-band quantum transport calculations at a reasonable computational cost and naturally allows the insertion of elastic and inelastic scattering mechanisms.

First, the talk will focus on assessing the electrical resistance of Schottky and ohmic contacts between (semi)metals and semiconducting 2D materials, such as monolayer MoS₂, and will discuss strategies to reduce contact resistances. Finally, self-consistent simulations of FETs based on realistic metal/2D material contacts, as well as cold-source electron devices, will be presented as illustrative applications.

Dr. Hong-Hyun Park（Samsung Semiconductor Inc. USA）

Simulation Development for Advanced Logic Technology at an IDM Company: Models and Tools Built to Support Real Device Issues

Atomistic and quantum-mechanical device simulation has traditionally been associated with academic research groups. This talk offers a somewhat different perspective—a retrospective of more than a decade of simulation model and simulator development carried out inside an IDM company, shaped by the issues encountered on the technology development floor. Most of this work was motivated less by a research agenda than by concrete questions from device and process engineers trying to understand why a real transistor behaved the way it did. In the early 2010s, strain effects in advanced FinFETs were difficult to capture with continuum tools alone, which led us to develop a multiscale valence force field (VFF) and finite element framework. As SiGe channels entered the roadmap, mobility estimates without fitting parameters were needed, and an empirical tight-binding plus VFF flow was put together to provide them. With gate-length scaling toward 7 nm and below, source-to-drain tunneling, ballisticity, and short-channel behavior became hard to diagnose with classical TCAD, which motivated the in-house development of a non-equilibrium Green's function (NEGF) simulator, gradually extended to vertically stacked silicon nanowire and nanosheet gate-all-around devices to help guide real process splits. More recent gate-stack questions—effective work-function tuning, interface dipoles, dielectric response—pushed the work toward density functional tight binding (DFTB) at the full gate-stack scale. The DFTB framework has evolved to relax atomic structures under finite bias and external electric field, which has allowed us to begin simulating dielectric permittivity in realistic gate stacks and to improve the fidelity of 2D-channel FET simulation. Looking back, the common thread is less a single physical theme than a way of working: trying to build the simulation capability that the next device generation seemed to need, one technology generation at a time.

Prof. Christoph Jungemann（RWTH Aachen University, Germany）

Semiclassical Modeling of Electron Transport in Semiconductor Devices based on the Boltzmann Equation

In the hierarchy of simulation tools for semiconductor device simulation the Boltzmann equation (BE) sits between the full quantum transport models (e.g. NEGF) and TCAD (e.g. DD). While scattering and band structures are calculated by quantum mechanical means, electron transport is essentially classical. This approximation has the advantage that larger devices in more complex situations (e.g. harmonic distortion in a power amplifier) can be simulated. On the other hand, the stringent approximations of the TCAD models (e.g. macroscopic transport parameters) are avoided, and the BE model is based on a few fundamental parameters for scattering and band structures which can be derived from ab initio calculations or fundamental experiments. A broad spectrum of applications of the BE are presented to exemplify its versatility: transport in III-V HBTs, THz photoionization of acceptors in silicon at 4K by coupled simulation of the BE and Maxwell’s equations, electronic noise in SiGe HBTs, magneto-transport in silicon inversion layers etc.

Prof. Junichiro Shiomi（University of Tokyo, Japan）

Multiscale Phonon Transport Modeling and Semiconductor Thermal Management

Predictive thermal management of semiconductor devices requires modeling heat transport across multiple length scales, from atomic vibrations to device-scale heat flow. This talk will present a multiscale framework combining first-principles anharmonic lattice dynamics, atomistic Green’s function calculations, and Monte Carlo simulations of the phonon Boltzmann transport equation to predict thermal transport in nanostructured materials and devices. Recent international round-robin studies and the development of the anharmonic phonon database (Phonix) will be introduced as efforts toward reliable and accessible thermal conductivity data. Finally, I will discuss emerging challenges in advanced semiconductor technologies, where coherent modulation of phonon states, altered phonon propagation, and enhanced electron–phonon interactions may fundamentally change heat dissipation mechanisms and require new approaches to thermal management.

Part AProcess Simulation